ECE 1387:

CAD For Digital Circuit Synthesis and Layout

J. Anderson
September 2013

About the Course Paper

  • The paper is a critical assessment of 3-4 papers in a chosen CAD area.  You must consult with the instructor on the topic you choose by mid-November at the latest.  Potential topics are given below.
  • Read 6-7 papers in your CAD topic area; choose 3-4 to cover in your paper.
  • Paper length: maximum 3000 words (hard limit with penalty for exceeding).  You'll need to be economical with your words.
  • Suggested paper section outline:
    • Introduction
      • Place your topic in the context of the overall synthesis flow.
    • Problem definition
      • Precisely define the problem, e.g., inputs, outputs, basic function, etc.
    • 3-4 different approaches
      • Give the essence of each approach, not the complete details.  (Convince me that you understand the approaches.)
    • Future work
      • Highlight what remains to be solved.
  • Reference style should be consistent throughout, similar to that appearing in typical academic papers.
  • The paper appearance should in be two-column single-spaced format, similar to that of typical academic papers.
  • NOTE: Paper must be your own words; no plagiarism.

Where To Find CAD Research Papers

In general, some of the places to look for CAD papers are:
  • IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD).
  • ACM Transactions on Design Automation of Electronic Systems.
  • International Conference on Computer-Aided Design (ICCAD).
  • Design Automation Conference (DAC).
  • European Design, Automation and Test Conference (DATE).
  • Asia-and-South Pacific Design Automation Conference (ASP-DAC)
  • International Symposium on Physical Design (ISPD).
  • International Symposium on Field Programmable Gate Arrays (FPGA), Int'l Conference on Field Programmable Logic (FPL), Int'l Conf. on Field-Programmable Technology (FPT).
Using a machine at UofT, you can access the IEEE and ACM digital libraries (go to,  In these libraries, you can find papers from all of the above conferences and journals in PDF format.

There are hundreds of papers published on CAD techniques every year.  For the class paper, you may select papers from the journals and conferences listed above; however, you are not limited to this and are free (and encouraged) to find/select your own papers. You are also welcome to consult with the instructor on the paper selection.

Suggested Topics for Course Paper

A few potential good topics for the research paper are given below.  The topics below are relatively well-developed, meaning that for these topics, you'll be able to find enough solid papers to survey for your own research paper.  However, the list below is certainly not exhaustive and you are welcome to choose your own, different topic.  You may want to consider choosing a CAD-related topic that will allow you to get a "jump start" on your intended research area.  Either way, you should discuss your selected topic with the instructor.

  • High-level synthesis.
    • Scheduling
    • Binding
    • FPGA architecture-specific approaches
  • Delay estimation in CAD.
  • Design for manufacturing.
    • CAD techniques that optimize timing yield or functional yield.
  • Power-aware CAD (you should narrow down to one step of the CAD flow (e.g. tech mapping) for one particular target technology (e.g. standard cell ASIC)).
  • Analytical placement algorithms.
  • Multi-level partitioning.
  • Multi-level partitioning-based placement algorithms.
  • Floorplanning algorithms/floorplan representations.
  • Statistical timing analysis.
  • Timing analysis crosstalk considerations in CAD.
  • Retiming/pipelining algorithms.
  • Floorplacement (integrated placement/floorplanning).
  • Wirelength estimation.
  • Congestion-aware placement.
  • Incremental synthesis (e.g., incremental placement, routing, etc.)
  • Enhancements to FM partitioning.
  • Technology mapping algorithms for standard cells.
  • Boolean flexibilities through Boolean relations or SPFDs.
  • Physical synthesis techniques.
    • Layout-driven logic replication.
    • Layout-driven retiming.
  • Transistor-level optimizations:
    • Automatic sizing.
    • Automatic threshold voltage selection.
  • FPGA-related CAD, any of:
    • FPGA routing algorithms.
    • Technology mapping.
    • FPGA placement.
    • Delay estimation.
    • Clustering.
    • Physical synthesis.