news

September 2017: Congrats to Joy on receiving the Best Paper Award at the 2017 Field-Programmable Logic and Applications (FPL) conference in Ghent, Belgium for her paper, "Automated Generation of Banked Memory Architectures in the High-Level Synthesis of Multi-Threaded Software," Well done!

September 2017: HEART 2018 will be held in Toronto in June 2018! The 9th annual Int'l Symp. on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART) deals with all aspects of compute acceleration. Conference website.

August 2017: Congrats to Safeen on his issued United States Patent on charge recycling! "Semiconductor Integrated Circuit," Tamura, Fujisawa, Fujimoto, Huda, Anderson.

July 2017: Congrats to Safeen on completing his Ph.D.! Well done Dr. Huda!

Congrats to Joy on completing her M.A.Sc.!

July 2017: Open-source CGRA-ME framework for coarse-grained reconfigurable architecture (CGRA) modelling and exploration is beta released! Link

June 2017: Congrats to Joy on her article accepted for publication in FPL 2017 to be held at Ghent, Belgium in September! "Automated Generation of Banked Memory Architectures in the High-Level Synthesis of Multi-Threaded Software," Chen, Anderson.

Congrats to Jin Hee, Brett and Lanny on their paper (on neural network inference acceleration) accepted for publication in IEEE SOCC 2017 to be held at Munich, Germany in September! "FPGA-Based CNN Inference Accelerator Synthesized from Multi-Threaded C Software," Kim, Grady, Lian, Brothers, Anderson.

June 2017: Congrats to Xander and co-authors Nori, Allan, Jim and Jin Hee, on the accepted IEEE ASAP 2017 paper: Chin, Sakamoto, Rui, Zhao, Kim, Hara-Azumi, Anderson, "CGRA-ME: A Unified Framework for CGRA Modelling and Exploration." The IEEE Int'l Conf. on Application-specific Systems, Architectures and Processors will be held in July in Seattle.

June 2017: Congrats to James on his journal paper accepted to IEEE Transactions on VLSI! Choi, Brown, Anderson, "From Pthreads to Multi-core Hardware Systems in LegUp High-Level Synthesis for FPGAs."

April 2017: Prof. Anderson will be co-teaching a one-week Heterogeneous Accelerator Summer School in Harbin, China from 24-29 July. Graduate students working in the area are encouraged to apply by the 22 May deadline. More information is here.

April 2017: Jin Hee's journal article appears this month in ACM Trans. on Reconfigurable Technology and Systems: "Synthesizable Standard Cell FPGA Fabrics Targetable by the Verilog-to-Routing CAD Flow." Congrats! (PDF).

March 2017: Congrats to Safeen on his accepted manuscript to IEEE Transactions on VLSI! Huda, Anderson, "Leveraging Unused Resources for Energy Optimization of FPGA Interconnect".

February 2017: Press release for the ACM FPGA 2017 conference to be held February 22-24 in Monterey, CA.

February 2017: Congrats to Eric LaForest on his paper accepted to the journal ACM Transactions on Reconfigurable Technology and Systems! "Microarchitectural Comparison of the MXP and Octavo Soft-Processor FPGA Overlays," LaForest and Anderson. Well done Eric!!

January 2017: Congrats to Noriaki Sakamoto on his accepted journal paper in IEEE Embedded Systems Letters (ESL)! "Subleq- : An Area-Efficient Two-Instruction-Set Computer," Sakamoto, Ahmed, Anderson, Hara-Azumi. Well done!

December 2016: We are looking for enthusiastic, driven new graduate students to join the group in 2017 to contribute to exciting projects on FPGA architecture, CAD and LegUp high-level synthesis. If you are interested in these topics and have strong skills in computer hardware, data structures and algorithms, please do get in touch.

November 2016: Congrats to Jin Hee on her accepted ACM TRETS journal publication! Kim, Anderson, "Synthesizable Standard Cell FPGA Fabrics Targetable by the Verilog-to-Routing (VTR) CAD Flow" (PDF).

>October 2016: Prof. Anderson will deliver a keynote talk at the 2016 IEEE Int'l Conference on Field-Programmable Technology (FPT) to be held at Xi'an, China in December (link).

September 2016: Congrats to James Jongsok Choi on successfully defending his Ph.D. thesis! Well done Dr. Choi!

September 2016: ECE1387 -- CAD for Digital Circuit Synthesis and Layout will commence on Friday September 16 from 5-7pm in GB221. Interested students should sign up at this link.

July 2016: Consider submitting a paper to the 2017 ACM Int'l Symposium on Field-Programmable Gate Arrays, to be held in Monterey, Calif, in February 2017. The Call for Papers is now posted! We are aiming to have a special session on the potential role for FPGAs in deep learning. Papers are due September 18. Link

May 2016: Welcome to Yuta Otsuka, a visiting graduate student researcher from Tohoku University, Sendai, Japan, who will be spending 10 months at UofT working with us.

May 2016: Congrats to James and Lanny on their accepted ASAP paper, "A Unified Software Approach to Specify Pipeline and Spatial Parallelism in FPGA Hardware"! The 2016 IEEE Int'l Conference on Application-specific Systems, Architectures and Processors (ASAP) will be held at London, UK in July.

May 2016: Prof. Anderson will be co-teaching (with other great instructors from around the world) a course in Hong Kong this summer on Performance-Aware Programming for Application Accelerators. Please consider joining this 1-week course from 18-22 July at the University of Hong Kong. Link

February 2016: Congrats to Safeen on the invited paper in the ACM Int'l Symposium on Physical Design (ISPD). Huda, Anderson, "Power Optimization of FPGA Interconnect Via Circuit and CAD Techniques". ISPD 2016 will be held in Santa Rosa, CA, in April 2016. Link

November 2015: Congrats to Andrew, James, Blair, Joy, Julie, and all the authors on the joint journal paper accepted to IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), including our collaborators from TU Milano and TU Delft! "A survey and comparison of FPGA high-level synthesis tools," Nane, Sima, Ferrandi, Pilato, Choi, Fort, Canis, Chen, Hsiao, Brown, Anderson, Bertels.

November 2015: Congrats to Safeen on his accepted ACM FPGA 2016 paper! Huda, Anderson, "Towards PVT-tolerant glitch-free operation in FPGAs". The ACM Int'l Symposium on FPGAs will be held at Monterey, CA in February 2016.

October 2015: Paper accepted to DATE 2016! Anderson, Hara-Azumi, Yamashita, "Effect of LFSR Seeding, Scrambling and Feedback Polynomial on Stochastic Computing Accuracy". The IEEE/ACM Design Automation and Test in Europe Conference will be held in Dresden, Germany, in March 2016.

September 2015: Congrats to James on his accepted FPT 2015 paper: "Resource and Memory Management Techniques for the High-Level Synthesis of Software Threads into Parallel FPGA Hardware," Choi, Brown, Anderson. The IEEE Int'l Conf. on Field-Programmable Technology will be held in New Zealand, in December 2015.

September 2015: Welcome to ECE1387: CAD for Digital Circuit Synthesis and Layout. Website

August 2015: LegUp 4.0 is released! Try out the long-awaited latest version of our FPGA high-level synthesis tool. Congrats to Andrew, James, Blair, Bain, Lanny, Joy, Julie, Jenny, Mathew, and Jeff! Link

August 2015: Well done everyone on the forthcoming book chapters!
Huda, Anderson, “Circuits and architectures for low-power FPGAs,” chapter in Reconfigurable Logic: Architecture, Tools and Applications, to be published by CRC Press, 2015.
Canis, Choi, Fort, Syrowik, Lian, Chen, Hsiao, Goeders, Brown, Anderson, “LegUp high-level synthesis,” chapter in FPGAs for Software Engineers, to be published by Springer, 2015.

July 2015: Welcome to Noriaki Sakamoto, a graduate student from Tokyo Institute of Technology visiting us for the rest of the summer.

July 2015: Paper accepted to IEEE EUC 2015 to be held at Porto, Portugal in October: Ahmed, Sakamoto, Anderson, Hara-Azumi, "Synthesizable-from-C Embedded Processor Based on MIPS-ISA and OISC." Congrats Tanvir and Nori!

June 2015: Congratulations to Xander and all on the journal paper accepted to IEEE Transactions on VLSI! Chin, Luu, Huda, Anderson, "Hybrid LUT/Multiplexer FPGA Logic Architectures".

June 2015: Congratulations to Jin Hee on her accepted paper at the 2015 Int'l Conf. on Field-Programmable Logic and Applications (FPL) to be held at London, UK in September! Kim, Anderson, "Synthesizable FPGA Fabrics Targetable by the Verilog-to-Routing (VTR) CAD Flow".

April 2015: US Patent issued on multi-threaded parallel programming leveraging a combination of spin locks and sleep states: Anderson, Ahmed and Kalman, "Thread synchronization by transitioning threads to spin lock and sleep state" (PDF)

April 2015: The International Conference on Field-Programmable Logic and Applications will be held in September at London, UK. Prof. Anderson is Chairing the Architectures and Technologies Track. Please join us at London in September!

February 2015: The deadline is fast approaching for the IEEE International Symposium on Application-Specific Systems, Architectures and Processors (ASAP) which will be in Toronto in July. Please consider submitting a paper. The Call for Papers is here.

December 2014: The IEEE International Symposium on Application-Specific Systems, Architectures and Processors (ASAP) will be in Toronto in July 2015. Please consider submitting a paper. The Call for Papers is now available.

December 2014: We are looking for 2-3 ECE or EngSci undergraduate researchers from UofT for summer 2015, to work on coarse-grained FPGA architecture and high-level synthesis. Please email your CV and transcript to Prof. Anderson if you are interested.

December 2014: Congratulations Marcel on receiving the Best Paper Award at FPT 2014 in Shanghai, China, for his article, "Design re-use for compile time reduction in FPGA high-level synthesis flows"!

November 2014: We are delivering a tutorial on high-level synthesis for FPGAs at the 2015 Asia-South Pacific Design Automation Conference (ASP-DAC), to be held at Tokyo, Japan in January. Please consider joining us if you will be in the region. Link

November 2014: Congrats to Stefan, Andrew and Ryoya on the accepted DATE 2015 paper! Stefan Hadjis, Andrew Canis, Ryoya Sobue, Yuko Hara-Azumi, Hiroyuki Tomiyama, and Jason Anderson, "Profiling-Driven Multi-Cycling in FPGA High-Level Synthesis," to appear at Design, Automation & Test in Europe (DATE), Grenoble, France, March 2015.

October 2014: The IEEE International Symposium on Application-specific Systems, Architectures and Processors (ASAP) will be held in Toronto, Canada in July 2015. The papers will be due in Feburary 2015 (date TBA). Please consider submitting an article, and joining us for the conference! Link

October 2014: Check out our new YouTube video about how to use LegUp high-level synthesis! Credit goes to Lanny Lian for creating the animations and annotations. Link

October 2014: Congratulations to Eric and Marcel for having their papers accepted to the IEEE Int'l Conf. on Field-Programmable Technology to be held at Shanghai, China in December. "Design Re-Use for Reduced Compile Time in FPGA High-Level Synthesis Flows" (Gort, Anderson), and "Approaching Overhead-Free Execution on FPGA Soft-Processors," (LaForest, Anderson, Steffan)! Link

September 2014: Welcome to new group members, Joy Chen and Julie Hsiao, who will be contributing to our high-level synthesis project working on visualization and optimization.

September 2014: LegUp high-level synthesis wins the Community Award at the 2014 Int'l Conference on Field-Programmable Logic and Applications (FPL) held at Munich, Germany, for "authors who have made a significant contribution to the community by providing some material or knowledge in an open format that benefits the rest of the community". Link

July 2014: We will be talking about LegUp high-level synthesis at the 1st Int'l Workshop on FPGAs for Software Programmers, which will be held Sept 1 at Munich, Germany, in conjunction with FPL 2014. Link

June 2014: We will be talking about LegUp high-level synthesis at the upcoming Big Data Workshop on July 3 at UofT. If you are around UofT on that day, and interested in the topic, please consider joining us. Link

June 2014: Congratulations to Andrew and Nazanin on their accepted FPL papers! The Int'l Conference on Field-Programmable Logic and Applications (FPL) 2014 will be held in September at Munich, Germany. N. Calagar, S. Brown, J. Anderson, "Source-Level Debugging for FPGA High-Level Synthesis". A. Canis, J. Anderson, S. Brown, "Modulo SDC Scheduling with Recurrence Minimization in High-Level Synthesis".

May 2014: We will present an invited paper on LegUp HLS at the IEEE Int'l Conference on Embedded and Ubiquitous Computing (EUC) to be held at Milan, Italy in August: "Automating the Design of Processor/Accelerator Embedded Systems with LegUp High-Level Synthesis".

April 2014: Congrats to Jenny, Lanny, James, Andrew, Nazanin, on the accepted ACM TRETS journal article, "The Effect of Compiler Optimizations on High-Level Synthesis-Generated Hardware".

April 2014: Congrats to Jason Luu and all the authors on the VTR article accepted to ACM TRETS, "VTR 7.0: Next generation architecture and CAD system for FPGAs".

April 2014: Prof. Anderson receives the Ontario Early Researcher Award from the Ministry of Research and Innovation. Link

March 2014: Kudos to all of the authors of the accepted FCCM 2014 paper, including Jason Luu and Safeen! "On Hard Adders and Carry Chains in FPGAs," Luu, McCullough, Wang, Huda, Bo, Chiasson, Kent, Anderson, Rose, Betz. The conference will be held in May at Boston, MA.

March 2014: Congrats to Safeen for receiving the Best Paper award at the 2014 ACM Int'l Symposium on FPGAs! "Optimizing effective interconnect capacitance for FPGA power reduction." (PDF)

January 2014: Congrats to Tahir on having his paper accepted to GPGPU7 to be held in March at Salt Lake City! "Power modeling for heterogeneous processors" (Diop, Enright Jerger, Anderson) Link

January 2014: The early registration deadline for ACM FPGA 2014 is Feb 6. ACM FPGA is one of the premiere forums for state-of-the-art advances in all aspects of FPGA technology. Please join us in Monterey, California from Feb 26-28. Link

January 2014: Article on LegUp in the ECE Annum Year-in-Review Magazine!

January 2014: Consider submitting a paper to the IEEE Int'l Symposium on Field-Programmable Custom Computing Machines (FCCM) to be held in May 2014 at Boston, MA. Link

December 2013: Congrats to the winners, finalists, and participants in the APS105 Connect6 competition! We have some amazingly talented first-year engineers. Read about it here!

December 2013: Congrats to Jason Luu and Safeen for having their papers accepted to the 2014 ACM Int'l Symposium on FPGAs to be held at Monterey, CA in February! "Towards Interconnect-Adaptive Packing for FPGAs" (Luu, Rose, Anderson), "Optimizing Effective Interconnect Capacitance for FPGA Power Reduction" (Huda, Anderson, Tamura).

October 2013: Congrats everybody on the accepted FPT 2013 Design Competition paper! Cai, Wang, Lian, Canis, Choi, Fort, Miao, Zhang, Calagar, Brown, Anderson, "From C to Blokus Duo with LegUp High-Level Synthesis."

October 2013: Congrats to Edgar on his accepted IEEE ReConFig 2013 paper to be presented in December at Cancun! "Leakage Power Reduction in FPGA DSP Circuits Through Algorithmic Noise Tolerance," (Mora-Sanchez, Anderson).

October 2013: Congrats to James, Xander and Ana on having their papers accepted to the IEEE FPT 2013 conference to be held at Kyoto, Japan in December! "From Software Threads to Parallel Hardware in High-Level Synthesis for FPGAs" (Choi, Anderson, Brown), "A Case for Hardened Multiplexers in FPGAs" (Chin, Anderson), "Bitwidth-Optimized Hardware Accelerators with Software Fallback" (Klimovic, Anderson).

August 2013: ECE1387: CAD for Circuit Synthesis and Layout will commence on Friday September 13, 5-7pm in GB119. Link

August 2013: Consider submitting a paper to the 2014 ACM Int'l Symposium on FPGAs to be held at Monterey, California in February. Papers are due September 20. Link

July 2013: We will present an invited talk and paper at the 2013 IEEE/ACM Int'l Conference on Compilers Architecture and Synthesis for Embedded Systems (CASES) to be held at Montreal in October: "From Software to Accelerators with LegUp High-Level Synthesis".

July 2013: Prof. Anderson was promoted to Associate Professor with tenure. Sincere thanks to my terrific graduate students, undergrad students, and colleagues at UofT and around the world!

June 2013: Congrats to Tahir and Steven on having their paper accepted to the IEEE Int'l Symposium on Modeling, Analysis and Simulation of Computer and Telecommunications Systems (MASCOTS) to be held at San Francisco in August! T. Diop, S. Gurfinkel, J. Anderson, N. Enright Jerger, "DistCL: A framework for the distributed execution of OpenCL kernels".

May 2013: Congrats to Safeen for having his paper accepted to the IEEE Int'l Conference on Field-Programmable Logic and Applications (FPL) to be held at Porto, Portugal in September: S. Huda, J. Anderson, H. Tamura, "Charge Recycling for Power Reduction in FPGA Interconnect".

May 2013: Congratulations to Safeen Huda for winning a Best Teaching Assistant Award!

April 2013: Prof. Anderson wins Faculty of Applied Science and Engineering Early Career Teaching Award. (press)

February 2013: Congrats to Jenny, Lanny, Andrew, James and Ryan on the accepted FCCM 2013 paper! The IEEE Int'l Symposium on Field-Programmable Custom Computing Machines (FCCM) will be held at Seattle from April 28-30. Q. Huang, R. Lian, A. Canis, J. Choi, R. Xi, S. Brown, J. Anderson, "The effect of compiler optimizations on high-level synthesis for FPGAs".

February 2013: Please join us for the LegUp tutorial on Monday February 11 at the ACM FPGA Symposium in Monterey, California. The tutorial will be "hands on" and interactive. Learn more and see how to download LegUp to your laptop in advance here. The time and location is here.

December 2012: We will deliver a tutorial on LegUp at the 2013 ACM FPGA symposium in Monterey, CA on February 11: "High-Level Synthesis with LegUp: A Crash Course for Users and Researchers". Learn more about it here.

December 2012: Congrats to Andrew on his accepted DATE 2013 paper, "Multi-Pumping for Resource Reduction in FPGA High-Level Synthesis."

November 2012: Congrats to Bill on his accepted IEEE TCAD journal paper: B. Teng and J. Anderson, "Latch-based performance optimization for FPGAs".

October 2012: The 2013 IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM) will be held at Seattle, Washington in April 2013. Link

September 2012: Congrats to Marcel on his accepted IEEE/ACM ASP-DAC 2013 paper. ASP-DAC will be held at Yokohama, Japan in January 2013: M. Gort, J.H. Anderson, "Range and bitmask analysis for hardware optimization in high-level synthesis".

September 2012: ECE1387: CAD for Digital Circuit Synthesis and Layout will commence on September 14 at 4pm in BA4164. Course website

August 2012: Welcome to Ryoya Sobue who is visiting the group from Ritsumeikan University in Japan. Ryoya is contributing to the LegUp HLS project.

July 2012: Demo papers and PhD forum papers for IEEE FPT 2012 (to be held at Seoul) are due on August 30.

June 2012: Papers for FPT 2012 (to be held at Seoul) are due in just one week on June 22.

June 2012: Congrats to Marcel on his accepted FPL 2012 paper!

April 2012: Prof. Anderson receives the 2012 Gordon R. Slemon Award for Excellence in the Teaching of Design! He also receives a Departmental Teaching Award for Excellence in Undergraduate Teaching in the Fall 2011 Term!

Prof. Anderson is Program Co-Chair for the 2012 IEEE Int'l Conference on Field-Programmable Technology (FPT) to be held Seoul National University, Seoul, Korea in December. Please submit your best work for consideration -- papers are due in early June.

March 2012: Consider submitting a paper to the IEEE Int'l Conf. on Very Large Scale Integration (VLSI-SoC 2012), to be held at Santa Cruz, CA in October 2012. Papers are due April 9 see: PDF.

February 2012: Paper accepted to appear in the 2012 IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM)! Congrats James, Andrew and Kevin! "Impact of cache architecture on performance and area of FPGA-based processor/parallel-accelerator systems".

December 2011: New release of LegUp -- our open source high-level synthesis tool. LegUp 2.0 incorporates many enhancements, including more sophisticated resource sharing and scheduling, as well as significant code re-factoring that will make it easier for researchers to modify and experiment with the tool.

December 2011: The 2012 International Symposium on Field-Programmable Custom Computing Machines (FCCM 2012) will be held at Toronto, Canada from April 29-May 1, 2012. Consider submiting a paper!

December 2011: Prof. Anderson is on the program committee for the 2012 Reconfigurable Architectures Workshop to be held at Shanghai, China. Please consider submitting a paper!

November 2011: Several papers accepted to upcoming conferences. Congrats to all of the students involved: Warren, Stefan, Andrew, James, Kevin, Zissis, Jason, Opal!!

  • Z. Poulous, T. Yang, J.H. Anderson, A. Veneris, "Leveraging reconfigurability to raise productivity in FPGA functional debug," to appear in the IEEE Design Automation and Test of Europe (DATE) Conference, to be held at Dresden, Germany, March 2012.
  • W. Shum, J.H. Anderson, "Analyzing and predicting the impact of CAD algorithm noise on FPGA speed performance and power," to appear in the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, to be held at Monterey, CA, February 2012.
  • S. Hadjis, A. Canis, J.H. Anderson, J. Choi, K. Nam, S. Brown. T. Czajkowski, "Impact of FPGA architecture on resource sharing in high-level synthesis," to appear in the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, to be held at Monterey, CA, February 2012.
  • J. Rose, J. Luu, K. Kent, C.-W. Yu, J.H. Anderson, O. Densmore, P. Jamieson, "The VTR project: architecture and CAD for FPGAs from Verilog to Routing," to appear in the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, to be held at Monterey, CA, February 2012.

September 2011: ECE1387: CAD for Digital Circuit Synthesis and Layout will commence on Friday September 16, 4:30-6:30 in BA2135.

September 2011: Best paper award at FPL 2011 for "Reducing FPGA Router Run-Time Through Algorithm and Architecture". Congrats Marcel!

August 2011: Best paper nomination at FPL 2011 for "Reducing FPGA Router Run-Time Through Algorithm and Architecture". Congrats Marcel!

July 2011: Paper accepted to IEEE Transactions on Computer-Aided Design (TCAD) of Integrated Circuits and Systems. Congrats Marcel! M. Gort, J. Anderson, "Accelerating FPGA Routing Through Parallelization and Engineering Enhancements".

June 2011: Paper accepted to the IEEE Int'l Conference on Application-specific, Systems, Architectures and Processors (ASAP) to be held at Santa Monica, CA in September 2011. This work is part of our LegUp high-level synthesis tool. Congratulations Mark! M. Aldham, J. Anderson, S. Brown and A. Canis, "Low-Cost Hardware Profiling or Run-time and Energy in FPGA Embedded Processors".

May 2011: Two articles accepted to the IEEE FPL 2011 conference to be held at Crete, Greece in September. Great work Bill and Marcel! M. Gort and J. Anderson, "Reducing FPGA Router Run-Time Through Algorithm and Architecture" and B. Teng and J. Anderson, "Latch-Based Performance Optimization for FPGAs".

May 2011: Prof. Anderson is the design competition co-chair for the IEEE FPT 2011 conference. Please consider participating!

May 2011: Paper accepted to the IEEE/ACM Int'l Symposium on Low Power Electronics and Design (ISLPED) to be held at Fukuoka, Japan in August 1-3, 2011. Congratulations Warren! W. Shum and J. Anderson, "FPGA Glitch Power Analysis and Reduction".

May 2011: Prof. Anderson receives departmental teaching award for ECE 241 Digital Systems.