united states patents

H. Tamura, J.H. Anderson, S. Huda, H. Fujimoto, "Method for designing semiconductor integrated circuit and program," US Patent #9,213,796, Issued December 2015.

J.H. Anderson, T. Ahmed, S. Kalman, “Thread synchronization by transitioning threads to spin lock and sleep state,” US Patent #9,003,413, Issued April 2015.

G. Jain, V. Verma, T. Ahmed, S. Kalman, S. Kwatra, C. Kingsley, J.H. Anderson, S. Das, "Multi-threaded deterministic router," US Patent #8,671,379, Issued March 2014.

G. Jain, V. Verma, T. Ahmed, S. Kalman, S. Kwatra, C. Kingsley, J.H. Anderson, S. Das, ``Multi-threaded deterministic router,'' US Patent #8,312,409, Issued November 2012.

J.H. Anderson, Q. Wang, "Method of and system for generating a logic configuration for an integrated circuit," US Patent #8,205,180, Issued June 2012.

Q. Wang, J.H. Anderson, S. Gupta, "Method and apparatus for reducing clock signal power consumption within an integrated circuit," US Patent #8,201,127, Issued June 2012.

H. Xu, V. Verma, A. Rahut, J.H. Anderson, S. Kalman, "Patterns for routing nets in a programmable logic device," US Patent #7,797,665, Issued September 2010.

J.H. Anderson, Q. Wang, "Method for technology mapping considering Boolean flexibility, " US Patent #7,725,047, Issued June 2010.

V. Verma, A. Rahut, S.K. Nag, J.H. Anderson, R. Jayaraman, "Method and apparatus for facilitating signal routing within a programmable logic device," US Patent #7,725,868, Issued May 2010.

J.H. Anderson, M. Chirania, S. Gupta, P. Costello, "Method of reducing power of a circuit," US Patent #7,653,891, Issued January 2010.

T. Jang, K. Chung, J.H. Anderson, Q. Wang and S. Gupta, "Method and apparatus for power optimization using don't care conditions of configuration bits in lookup tables," US Patent #7,603,646, Issued October 2009.

Q. Wang, R. Aggarwal and J.H. Anderson, "Processing constraints in computer-aided design for integrated circuits," US Patent #7,555,734, Issued June 2009.

J. Saunders, K. Anandh, G. Stenz, S.K. Nag and J.H. Anderson, "Unified placer infrastructure," US Patent #7,398,496, Issued July 2008.

V. Verma, A. Rahut, S.K. Nag and J.H. Anderson, “Method and apparatus for facilitating signal routing within a programmable logic device,” US Patent #7,306,977, Issued December 2007.

J.H. Anderson, S.K. Nag G. Stenz and S. Dasasathyan, "Method for application of network flow techniques under constraints," US Patent #7,143,380, Issued November 2006.

J.H. Anderson, S. Kalman and V. Verma, "Incremental routing in integrated circuit design," US Patent #7,134,112, Issued November 2006.

J.H. Anderson, S. Kalman and V. Verma, "Post-layout optimization in integrated circuit design," US Patent #7,111,268, Issued September 2006.

R. Kong and J.H. Anderson, "Method for computing and using future costing data in signal routing," US Patent #7,073,155, Issued July 2006.

J.H. Anderson and F.N. Najm, "Leakage power optimization for integrated circuits," US Patent #6,993,737, Issued January 2006.

J. Saunders, K. Anandh, G. Stenz, S.K. Nag and J.H. Anderson, "Unified placer infrastructure," US Patent #6,983,439, Issued January 2006.

G.-J. Nam, S. Kalman, J.H. Anderson, R. Jayaraman, S.K. Nag and J. Zhuang, "Method and apparatus for testing routability," US Patent #6,877,040, Issued April 2005.

J.H. Anderson, "Incremental placement of design objects in an integrated circuit design," US Patent #6,871,336, Issued March 2005.

S. Dasasathyan, G. Stenz, S.K. Nag and J.H. Anderson, "Placement of objects with partial shape restriction," US Patent #6,857,115, Issued February 2005.

R. Kong and J.H. Anderson, "Method for computing and using future costing data in signal routing," US Patent #6,851,101, Issued February 2005.

J.H. Anderson, J. Saunders, M. Chari, S. Nag and R. Jayaraman, "Method and apparatus for placement of input-output design objects into a programmable gate array," US Patent #6,625,795, Issued September 2003.

S. Nag, K. Chaudhary, J.H. Anderson, M. Chari and S. Kalman, "Method and apparatus for timing-driven implementation of a circuit design," US Patent #6,484,298, Issued November 2002.

J.H. Anderson, J. Saunders, M. Chari, S. Nag and R. Jayaraman, "Placement of input-output design objects into a programmable gate array supporting multiple voltage standards," US Patent #6,289,496, Issued September 2001.

book chapters

A. Canis, J. Choi, B. Fort, B. Syrowik, R.L. Lian, Y.-T. Chen, H. Hsiao, J. Goeders, S. Brown, J.H. Anderson, “LegUp high-level synthesis,” chapter in FPGAs for Software Engineers, Springer, 2015.

M. Hutton, V. Betz, J.H. Anderson, “FPGA synthesis and physical design,” chapter in Electronic Design Automation for Integrated Circuits, CRC Press, 2015.

S. Huda, J.H. Anderson, “Circuits and architectures for low-power FPGAs,” chapter in Reconfigurable Logic: Architecture, Tools and Applications, CRC Press, 2015.

refereed publications in conferences

H. Hsiao, J.H. Anderson, "Sensei: An Area-Reduction Advisor for FPGA High-Level Synthesis," to appear in the IEEE/ACM Design, Automation and Test in Europe Conference (DATE) to be held at Dresden, Germany, March 2018. (PDF)

S. Bansal, H. Hsiao, T. Czajkowski, J.H. Anderson, "High-Level Synthesis of Software-Customizable Floating-Point Cores," to appear in the IEEE/ACM Design, Automation and Test in Europe Conference (DATE) to be held at Dresden, Germany, March 2018. (PDF)

J. H. Kim, B. Grady, R. Lian, J. Brothers, J.H. Anderson, “FPGA-Based CNN Inference Accelerator Synthesized from Multi-Threaded C Software,” IEEE Int’l System-on-Chip Conference (SOCC), Munich, Germany, September, 2017. (PDF)

Y.-T. Chen, J.H. Anderson, "Automated Generation of Banked Memory Architectures in the High-Level Synthesis of Multi-Threaded Software," Int'l Conference on Field-Programmable Logic and Applications (FPL), Ghent, Belgium, September 2017. (PDF)

S. A. Chin, N. Sakamoto, A. Rui, J. Zhao, J. H. Kim, Y. Hara-Azumi, J.H. Anderson, "CGRA-ME: A Unified Framework for CGRA Modelling and Exploration," IEEE Int'l Conference on Application-specific Systems, Architectures and Processors (ASAP), Seattle, WA, July 2017. (PDF)

J. Choi, R. Lian, S. Brown, J.H. Anderson, "A Unified Software Approach to Specify Pipeline and Spatial Parallelism in FPGA Hardware," IEEE Int'l Conference on Application-specific Systems, Architectures and Processors, London, UK, July 2016. (PDF)

S. Huda, J.H. Anderson, "Power optimization of FPGA interconnect via circuit and CAD techniques," invited paper to appear in the ACM Int'l Symposium on Physical Design (ISPD), Santa Rosa, CA, April 2016. (PDF)

S. Huda, J.H. Anderson, "Towards PVT-tolerant glitch-free operation in FPGAs," ACM Int'l Symposium on Field-Programmable Gate Arrays (FPGA), Monterey, CA, February 2016. (PDF)

J.H. Anderson, Y. Hara-Azumi, S. Yamashita, "Effect of LFSR Seeding, Scrambling and Feedback Polynomial on Stochastic Computing Accuracy," ACM/IEEE Design Automation and Test in Europe Conference (DATE), Dresden, Germany, March 2016. (PDF)

J. Choi, S. Brown, J. Anderson, "Resource and Memory Management Techniques for the High-Level Synthesis of Software Threads into Parallel FPGA Hardware," IEEE Int'l Conference on Field-Programmable Technology (FPT), New Zealand, December 2015. (PDF)

T. Ahmed, N. Sakamoto, J.H. Anderson, Y. Hara-Azumi, "Synthesizble-from-C embedded processor based on MIPS-ISA and OISC," IEEE Int'l Conference on Embedded and Ubiquitous Computing (EUC), Porto, Portugal, October, 2015. (PDF)

J. Kim, J.H. Anderson, "Synthesizable FPGA fabrics targetable by the Verilog-to-Routing (VTR) CAD flow," Int'l Conference on Field-Programmable Logic and Applications (FPL), London, UK, September 2015. (PDF)

S. Hadjis, A. Canis, R. Sobue, Y. Hara-Azumi, H. Tomiyama, J. Anderson, "Profiling-driven multi-cycling in FPGA high-level synthesis," ACM/IEEE Design Automation and Test in Europe Conference (DATE), Grenoble, France, March 2015. (PDF)

M. Gort, J.H. Anderson, “Design re-use for compile time reduction in FPGA high-level synthesis flows,” IEEE International Conference on Field-Programmable Technology (FPT), Shanghai, China, December 2014. (PDF) (Best Paper Award!)

C.E. LaForest, J.H. Anderson, J.G. Steffan, “Approaching overhead-free execution on FPGA soft processors,” IEEE International Conference on Field-Programmable Technology (FPT), Shanghai, China, December 2014. (PDF)

N. Calagar, S. Brown, J.H. Anderson, “Source-Level debugging for FPGA high-Level synthesis,” IEEE International Conference on Field-Programmable Logic and Applications (FPL), Germany, September 2014. (PDF)

A. Canis, J.H. Anderson, S. Brown, “Modulo SDC scheduling with recurrence minimization in high-Level synthesis,” IEEE International Conference on Field-Programmable Logic and Applications (FPL), Munich, Germany, September 2014. (PDF)

B. Fort, A. Canis, J. Choi, N. Calagar, R. Lian, S. Hadjis, Y.T. Chen, M. Hall, B. Syrowik, T. Czajkowski, S. Brown, J.H. Anderson, “Automating the Design of Processor/Accelerator Embedded Systems with LegUp High-Level Synthesis,” IEEE International Conference on Embedded and Ubiquitous Computing (EUC), Milan, Italy, August 2014. (PDF)

J. Luu, C. McCullough, S. Wang, S. Huda, Y. Bo, C. Chiasson, K. Kent, J. Anderson, J. Rose and V. Betz, "On hard adders and carry chains in FPGAs," IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), Boston, MA, May 2014. (PDF)

T. Diop, N. Enright Jerger, J.H. Anderson, "Power modeling for heterogeneous processors," ACM Workshop for General Purpose GPU Computing (GPGPU), Salt Lake City, UT, March 2014. (PDF)

S. Huda, J.H. Anderson, H. Tamura, "Optimizing effective interconnect capacitance for FPGA power reduction," ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), pp. 11-20, Monterey, CA, Febuary 2014. (PDF) (Best Paper Award!)

J. Luu, J. Rose, J.H. Anderson, "Towards interconnect-adaptive packing for FPGAs," ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), pp. 21-30, Monterey, CA, Febuary 2014. (PDF)

J. Choi, J.H. Anderson, S. Brown, “From software threads to parallel hardware in FPGA high-level synthesis,” IEEE International Conference on Field-Programmable Technology (FPT), pp. 270-279, Kyoto, Japan, December 2013. (PDF)

A. Klimovic, J.H. Anderson, “Bitwidth-optimized hardware accelerators with software fallback,” IEEE International Conference on Field-Programmable Technology (FPT), pp. 136-143, Kyoto, Japan, December 2013. (PDF)

S. Chin, J.H. Anderson, “A case for hardened multiplexers in FPGAs,” IEEE International Conference on Field-Programmable Technology (FPT), pp. 42-49, Kyoto, Japan, December 2013. (PDF)

J. Cai, R. Lian, M. Wang, A. Canis, J. Choi, B. Fort, E. Miao, Y. Zhang, N. Calagar, S. Brown, J.H. Anderson, “From C to Blokus Duo with LegUp High-Level Synthesis,” IEEE International Conference on Field-Programmable Technology (FPT), pp. 46-49, Kyoto, Japan, December 2013. (PDF)

E. Mora-Sanchez, J.H. Anderson, “Leakage power reduction in FPGA DSP circuits through algorithmic noise tolerance,” IEEE International Conference on Reconfigurable Computing and FPGAs (ReConFig), Cancun, Mexico, December 2013.

A. Canis, J. Choi, B. Fort, R. Lian, Q. Huang, N. Calagar, M. Gort, J. Qin, T. Czajkowski, S. Brown, J. Anderson, "From software to accelerators with LegUp high-level synthesis," invited paper in the IEEE/ACM International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES), Montreal, Canada, October 2013. (PDF)

T. Diop, S. Gurfinkel, J. Anderson, N. Enright Jerger, "DistCL: A framework for the distributed execution of OpenCL kernels," IEEE Int'l Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS), San Francisco, August 2013. (PDF)

S. Huda, J. Anderson, H. Tamura, "Charge recycling for power reduction in FPGA interconnect," IEEE Int'l Conference on Field Programmable Logic and Applications (FPL), Porto, Portugal, September 2013. (PDF)

Q. Huang, R. Lian, A. Canis, J. Choi, R. Xi, S. Brown, J. Anderson, "The effect of compiler optimizations on high-level synthesis for FPGAs," IEEE Int'l Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 89-96, Seattle, WA, May 2013. (PDF). (Auto-generated recipies for the iteration, insertion, and insertion-3 method.)

A. Canis, J. Anderson, S. Brown, "Multi-pumping for resource reduction in FPGA high-level synthesis," IEEE/ACM Design Automation and Test in Europe Conference (DATE), pp. 194-197, Grenoble, France, March 2013. (PDF).

M. Gort, J. Anderson, "Range and bitmask analysis for hardware optimization in high-level synthesis," IEEE/ACM Asia-and-South Pacific Design Automation Conference (ASP-DAC), pp. 773-779, Yokohama, Japan, January 2013. (PDF).

M. Gort, J. Anderson, "Analytical placement for heterogeneous FPGAs," IEEE International Conference on Field Programmable Logic and Applications (FPL), pp. 143-150, Oslo, Norway, August 2012. (PDF).

J. Choi, K. Nam, A. Canis, J.H. Anderson, S. Brown, T. Czajkowski, "Impact of cache architecture on speed and area of FPGA-based processor/parallel-accelerator systems," IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 17-24, Toronto, Canada, April 2012. (PDF).

Z. Poulos, Y.S. Yang, J.H. Anderson, A. Veneris, B. Le, "Leveraging reconfigurability to raise productivity in FPGA functional debug," IEEE Design Automation and Test of Europe (DATE) Conference, pp. 292-295, Dresden, Germany, March 2012. (PDF).

W. Shum, J.H. Anderson, "Analyzing and predicting the impact of CAD algorithm noise on FPGA speed performance and power," ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA), pp. 107-110, Monterey, CA, February 2012. (PDF).

S. Hadjis, A. Canis, J.H. Anderson, J. Choi, K. Nam, S. Brown. T. Czajkowski, "Impact of FPGA architecture on resource sharing in high-level synthesis," ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA), pp. 111-114, Monterey, CA, February 2012. (PDF)

J. Rose, J. Luu, K. Kent, C.-W. Yu, J.H. Anderson, O. Densmore, P. Jamieson, "The VTR project: architecture and CAD for FPGAs from Verilog to Routing," ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA), pp. 77-86, Monterey, CA, February 2012. (PDF)

M. Aldham, J.H. Anderson, S. Brown, A. Canis, "Low-cost hardware profiling of run-time and energy in FPGA embedded processors," IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), pp. 61-68, Santa Monica, CA, September 2011. (PDF)

B. Teng, J.H. Anderson, "Latch-based performance optimization for FPGAs,"IEEE International Conference on Field Programmable Logic and Applications (FPL), pp. 58-63, Crete, Greece, September 2011. (PDF)

M. Gort, J.H. Anderson, "Reducing FPGA router run-time through algorithm and architecture," IEEE International Conference on Field Programmable Logic and Applications (FPL), pp. 336-342, Crete, Greece, September 2011. (PDF (best paper award!)

W. Shum, J.H. Anderson, "FPGA glitch power analysis and reduction," IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pp. 27-32, Fukuoka, Japan, August 2011. (PDF)

A. Canis, J. Choi, M. Aldham, V. Zhang, A. Kammoona, J.H. Anderson, S. Brown, T. Czajkowski, "LegUp: High-level synthesis for FPGA-based processor/accelerator systems,"ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA), pp. 33-36, Monterey, CA, February 2011. (PDF)

J. Luu, J.H. Anderson, J. Rose, "Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect," ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA), pp. 227-236, Monterey, CA, February 2011. (PDF)

J.H. Anderson, Q. Wang, "Area-efficient FPGA logic elements: architecture and synthesis," IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 369-375, Yokohama, Japan, January 2011. (best paper nomination!) (PDF)

A. Rakhshanfar, J.H. Anderson, "An integer programming placement approach for FPGA clock power reduction," IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 831-836, Yokohama, Japan, January 2011. (PDF)

M. Gort, J.H. Anderson, "Deterministic multi-core parallel routing for FPGAs," IEEE International Conference on Field Programmable Technology (FPT), pp. 78-86, Beijing, China, 2010. (PDF)

S. Birk, J.G. Steffan, J.H. Anderson, "Parallelizing FPGA placement using transactional memory," IEEE International Conference on Field Programmable Technology (FPT), pp. 61-69, Beijing, China, 2010. (PDF) (best paper award!)

J.H. Anderson, C. Ravishankar, "FPGA power reduction by guarded evaluation," ACM/SIGDA International Conference on Field Programmable Gate Arrays (FPGA), pp. 157-166, Monterey, CA, 2010. (PDF)

J.H. Anderson, "A PUF design for secure FPGA-based embedded systems," IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 1-6, Taipei, Taiwan, 2010. (PDF) (VHDL download)

J.H. Anderson, Q. Wang, "Improving logic density through synthesis-inspired architecture," IEEE International Conference on Field-Programmable Logic and Applications (FPL), pp. 105-111, Prague, Czech Republic, 2009. (PDF)

S. Huda, M. Mallick, J.H. Anderson, "Clock gating architectures for FPGA power reduction," IEEE International Conference on Field-Programmable Logic and Applications (FPL), pp. 112-118, Prague, Czech Republic, 2009. (PDF)

Q. Wang, S. Gupta, J.H. Anderson, "Clock power reduction for Virtex-5 FPGAs" ACM/SIGDA International Conference on Field Programmable Gate Arrays (FPGA), pp. 13-22, Monterey, CA, February, 2009. (PDF)

T. Ahmed, P. Kundarewich, J.H. Anderson, B. Taylor, R. Aggarwal, "Architecture-specific packing for Virtex-5 FPGAs," pp. 5-13, ACM/SIGDA International Conference on Field Programmable Gate Arrays (FPGA), Monterey, CA, February, 2008. (PDF)

S. Gupta, J.H. Anderson, L. Farragher and Q. Wang, "CAD techniques for power optimization in Virtex-5 FPGAs," IEEE Custom Integrated Circuits Conference (CICC), pp. 85-88, San Jose, CA, 2007. (PDF)

J.H. Anderson and F.N. Najm, "Low-power programmable routing circuitry for FPGAs," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 602-609, San Jose, CA, 2004. (PDF)

J.H. Anderson and F.N. Najm, "A novel low-power FPGA routing switch," IEEE Custom Integrated Circuits Conference (CICC), pp. 719-722, Orlando, FL, 2004. (PDF)

J.H. Anderson, S. Nag, K. Chaudhary, S Kalman, C. Madabhushi and P. Cheng, "Run-time-conscious automatic timing-driven FPGA layout synthesis," International Conference on Field-Programmable Logic and Applications (FPL), pp. 168-178, Antwerp, Belgium, 2004. (PDF)

J.H. Anderson, F.N. Najm and T. Tuan, "Active leakage power optimization for FPGAs," ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA), pp. 33-41, Monterey, CA, 2004.

J.H. Anderson and F.N. Najm, "Interconnect capacitance estimation for FPGAs," IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 713-718, Yokohama, Japan, 2004.

J.H. Anderson and F.N. Najm, "Switching activity analysis and pre-layout activity prediction for FPGAs," ACM/IEEE International Workshop on System-Level Interconnect Prediction (SLIP), pp. 15-21, Monterey, CA, 2003.

J.H. Anderson and F.N. Najm, "Power-aware technology mapping for LUT-based FPGAs," IEEE International Conference on Field-Programmable Technology (FPT), pp. 211-218, Hong Kong, 2002. (PDF)

J.H. Anderson, J. Saunders, S. Nag, C. Madabhushi and R. Jayaraman, "A placement algorithm for FPGA designs with multiple I/O standards," International Conference on Field-Programmable Logic and Applications (FPL), LNCS 1896, Springer-Verlag, pp. 211-220, Villach, Austria, 2000. (PDF)

J.H. Anderson and S.D. Brown, "Technology mapping for large complex PLDs," ACM/IEEE Design Automation Conference (DAC), pp. 698-703, San Francisco, CA, 1998. (PDF)

J.H. Anderson and S.D. Brown, "An LPGA with foldable logic blocks," ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA), pp. 244-252, Monterey, CA, 1998. (PDF)

refereed journal publications

J. Choi, S. Brown, J.H. Anderson, "From Pthreads to Multi-core Hardware Systems in LegUp High-Level Synthesis for FPGAs," accepted to appear in IEEE Transactions on Very-Large Scale Integration Systems (TVLSI), June 2017. (PDF)

S. Huda, J.H. Anderson, "Leveraging Unused Resources for Energy Optimization of FPGA Interconnect," accepted to appear in IEEE Transactions on Very-Large Scale Integration Systems (TVLSI), March 2017. (PDF)

N. Sakamoto, T. Ahmed, J.H. Anderson, Y. Hara-Azumi, "SubleqΘ: A Two-Instruction-Set Computer," accepted to appear in IEEE Embedded Systems Letters, January 2017. (PDF)

C.E. LaForest, J.H. Anderson, "Evaluation of Overlay, HLS, and HDL FPGA Implementations," accepted to ACM Transactions on Reconfigurable Technology and Systems (TRETS), 2017 (PDF).

J. Kim, J.H. Anderson, "Synthesizable Standard Cell FPGA Fabrics Targetable by the Verilog-to-Routing (VTR) CAD Flow," ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 10, no. 2, April 2017 (PDF).

P. Leong, H. Amano, J.H. Anderson, K. Bertels, et al., "The first 25 years of the FPL conference – significant papers," accepted to appear in the ACM Transactions on Reconfigurable Technology and Systems (TRETS), 2016. (PDF)

R. Nane, V.-M. Sima, F. Ferrandi, C. Pilato, J. Choi , B. Fort, A. Canis, Y.T. Chen, H. Hsiao, S. Brown, J.H. Anderson, Koen Bertels, "A survey and evaluation of FPGA high-level synthesis tools," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), October 2016. (PDF)

S.A. Chin, J. Luu, S. Huda, J.H. Anderson, "Hybrid LUT/Multiplexer FPGA Logic Architectures," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 4, pp. 1280-1292, 2015 (PDF).

Q. Huang, R. Lian, A. Canis, J. Choi, R. Xi, S. Brown, J.H. Anderson, "The effect of compiler optimizations on high-level synthesis-generated hardware," ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 8, no. 3, May, 2015. (PDF)

J. Luu, G. Goeders, M. Wainberg, A. Summerville, T. Yu, K. Nasartschuk, M. Nasr, S. Wang, T. Liu, N. Ahmed, K. Kent, J.H. Anderson, J. Rose, V. Betz, "VTR 7.0: Next generation architecture and CAD system for FPGAs," accepted to appear in ACM Transactions on Reconfigurable Technology and Systems (TRETS), March, 2014.

B. Teng and J.H. Anderson, "Latch-based performance optimization for FPGAs," accepted to appear in IEEE Transactions on Computer-Aided Design for Integrated Circuits and Systems (TCAD), February 2012. (14 page manuscript).

M. Gort and J.H. Anderson, "A combined architecture/algorithm approach to fast FPGA routing," accepted to appear in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, May 2012.

A. Canis, J. Choi, M. Aldham, V. Zhang, A. Kammoona, J.H. Anderson, S. Brown, T. Czajkowski, "LegUp: Open source high-level synthesis for FPGA-based processor/accelerator systems", accepted to appear in ACM Transactions on Embedded Computing Systems (TECS), April 2012. (PDF)

C. Ravishankar, J.H. Anderson, A. Kennings, "FPGA power reduction by guarded evaluation considering logic architecture," accepted to appear in IEEE Transactions on Computer Aided Design for Integrated Circuits and Systems (TCAD), February 2012. (PDF)

M. Gort, J.H. Anderson, "Accelerating FPGA routing through parallelization and engineering enhancements", IEEE Transactions on Computer Aided Design for Integrated Circuits and Systems (TCAD), Vol. 31, No. 1, pp. 71-74, January 2012.

J. Anderson, Q. Wang, C. Ravishankar, "Raising FPGA logic density through synthesis-inspired architecture," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 20, No. 3, pp. 537-550, March 2012. (PDF)

T. Ahmed, P.D. Kundarewich, J.H. Anderson, "Packing techniques for Virtex-5 FPGAs," ACM Transactions on Reconfigurable Technology and Systems (TRETS), Vol 2, No. 3, September 2009. (PDF)

J.H. Anderson and F.N. Najm, "Low-power programmable FPGA routing circuitry," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 17, No. 8, pp. 1048-1060, 2009. (PDF)

J.H. Anderson and F.N. Najm, "Active leakage power optimization for FPGAs," IEEE Transactions on Computer-Aided Design for Integrated Circuits and Systems (TCAD), Vol. 25, No. 3, pp. 423-437, March 2006. (PDF)

J.H. Anderson and F.N. Najm, "Power estimation techniques for FPGAs," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 12, No. 10, pp. 1015-1027, October 2004. (PDF)

dissertation

J.H. Anderson, "Power optimization and prediction techniques for FPGAs," Ph.D. Thesis, Department of Electrical and Computer Engineering, University of Toronto, 2005. (PDF)